This invention pertains to synchronization of duplex processor equipment and more particularly to a circuit for continuously synchronizing duplex processor controllers.
In modern electronic switching, a great number of telephone subscribers are connected to the international switching network via computer controlled electronic switching systems. Such electronic switching systems typically have fault tolerant systems at critical points to insure continuous operation of the system. These switching offices have a reliability requirement due to the public policy of providing telephone service 24 hours a day on an uninterrupt basis. Since the central processing unit (CPU) is the heart of the switching system, the CPU arrangement must be a fault tolerant one. Typical solutions to this problem have been to provide redundant equipment. This redundant equipment must run synchronously, that is, each CPU must perform the same task at the same time. If the processors are not operated synchronously then, for a fault in one processor, service is temporarily interrupted while the other processor is placed on-line and active. In addition, other interface and control equipment which is operated by the central processors is also synchronously operated.
It is required that these processor controllers also operate synchronously and continuously monitor their synchronous operation. Furthermore, it is desirable that these processor controllers automatically and quickly resynchronize themselves for any detected lack of synchronization.
Typical synchronizing systems count clock pulses and modulate the resulting clock outputs by adding or deleting clock pulses, as required. The synchronization circuits which employ these pulse counting techniques are typically complex and difficult to maintain. Further, if a timing parameter is changed, the entire design of the counting circuit must be altered to reflect this change.